Optimized Design of Low-power Adiabatic Dynamic CMOS Logic Digital PWM using Clock Cut-off Circuit and Miniaturization for SSL Dimming System
نویسندگان
چکیده
In this paper, the low-power adiabatic dynamic CMOS logic (ADCL) digital pulse width modulation (PWM) has been designed for solid state lighting (SSL) dimming system. Architecture of ADCL digital 3-bit PWM is miniaturized. 60 transistors and 15 capacitors were reduced. Furthermore, the clock cut-off circuit which controls wake-up and sleep mode of ADCL DFFs is proposed. The power consumption of optimized ADCL digital PWM for all bit patterns is found to decrease by 54%.
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